Engineering:MASTAR MOSFET Model

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The MASTAR (Model for Analog Simulation of subThreshold, saturation and weak Avalanche Regions)[1][2] is an analytical model of Metal-Oxide Semiconductor Field-Effect Transistors, developed using the voltage-doping transformation (VDT) technique.[3][4][5][6] MASTAR offers good accuracy and continuity in current and its derivatives in all operation regimes of the MOSFET devices. The model has been successfully used in CAD/EDA simulation tools.[7]

The official ITRS definition of the acronym MASTAR is Model for Assessment of CMOS Technologies And Roadmaps.[8] This software[9][10][11] is developed by STMicroelectronics and is freely distributed on ITRS organization web site.

See also

References

  1. ↑ Skotnicki, T.; Merckel, G.; Denat, C. (1993). "MASTAR - A Model for Analog Simulation of Subthreshold, Saturation and Weak Avalanche Regions in MOSFETs". [Proceedings] 1993 International Workshop on VLSI Process and Device Modeling (1993 VPAD) (published May 14–15, 1993). pp. 146–147. doi:10.1109/VPAD.1993.724762. ISBN 0-7803-1338-0. 
  2. ↑ Skotnicki, T.; Denat, C.; Senn, P.; Merckel, G.; Hennion, B. (1994), "A new analog/digital CAD model for sub-halfmicron MOSFETs", Technical Digest., International Electron Devices Meeting: 165–168, December 11–14, 1994 
  3. ↑ Skotnicki, T.; Marciniak, W. (1986), "A new approach to threshold voltage modelling of short-channel MOSFETS", Solid-State Electronics 29 (11): 1115–1127, November 1986, doi:10.1016/0038-1101(86)90054-7, Bibcode: 1986SSEle..29.1115S 
  4. ↑ Skotnicki, T.; Merckel, G.; Pedron, T. (1988), "The voltage-doping transformation: a new approach to the modeling of MOSFET short-channel effects", IEEE Electron Device Letters 9 (3): 109–112, March 1988, doi:10.1109/55.2058, Bibcode: 1988IEDL....9..109S 
  5. ↑ Skotnicki, T.; Merckel, G.; Pedron, T. (1988), "A new punchthrough current model based on the voltage-doping transformation", IEEE Transactions on Electron Devices 35 (7): 1076–1086, June 1988, doi:10.1109/16.3367, Bibcode: 1988ITED...35.1076S 
  6. ↑ Skotnicki, T.; Merckel, G.; Pedron, T. (1989), "Analytical study of punchthrough in buried channel p-MOSFETs", IEEE Transactions on Electron Devices 36 (4): 690–705, April 1989, doi:10.1109/16.22474, Bibcode: 1989ITED...36..690S 
  7. ↑ Modeling MOS Devices Using the MASTAR Model with UTMOST III
  8. ↑ ITRS Models, ITRS, archived from the original on 2013-07-09, https://web.archive.org/web/20130709053354/http://www.itrs.net/models.html, retrieved 2013-03-15 
  9. ↑ Skotnicki, Tomasz; Boeuf, Frédéric (2004), "Optimal scaling methodologies and transistor performance", Published in Book "High Dielectric Constant Materials - VLSI MOSFET Applications" Edited by Howard R. Huff and David Gilmer Springer Series Microelectronics 16 
  10. ↑ Skotnicki, Thomas; Hutchby, James A.; King, Tsu-Jae; Wong, H.-S. Philip; Boeuf, Frederic (2005), "The Road To The End Of Cmos Scaling", IEEE Circuits and Devices Magazine 21 (1): 16–26, Jan–Feb 2005, doi:10.1109/MCD.2005.1388765 
  11. ↑ Skotnicki, Thomas; Fenouillet-Beranger, Claire; Gallon, Claire; Bœuf, Frederic; Monfray, Stephane; Payet, Fabrice; Pouydebasque, Arnaud; Szczap, Melanie et al. (2008), "Innovative materials devices and CMOS technologies for low-power mobile multimedia", IEEE Transactions on Electron Devices 55 (1): 96–130, January 2008, doi:10.1109/TED.2007.911338, Bibcode: 2008ITED...55...96S 




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